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Toshiba Develops 32-Megabit NAND Flash EEPROM

15 February, 1995


TOKYO -- Toshiba Corporation today announced that it has developed a 32-megabit NAND flash electrically erasable programmable read only memory (EEPROM). The new device is fabricated with 0.425 micrometer CMOS process technology and achieves a high speed access time of 28 nanoseconds with either single 3.3V or 5V power supply. The new device also offers the world's fastest data erasure operation of any EEPROM: single block erasure takes 2.5 milliseconds, while all blocks can be erased in only 5 milliseconds.

Flash memory is widely recognized as a promising alternative to disk-based storage, particularly in portable computers and personal digital assistants that require a combination of large memory capacity and portability. Toshiba has already mass-produced 16-megabit devices, and plans to start sample shipments of its new 32-megabit device this year.

The new technologies incorporated in the 32-megabit NAND flash memory will be announced tomorrow at the International Solid State Circuits Conference '95, in San Francisco, U.S.

Backgrounds of the new development:

An EEPROM is a non-volatile memory device -- a semiconductor chip that retains data even when its power supply is turned off, and which allows users to freely erase and replace data. EEPROMs offer advantages in size and weight, low power consumption and high resistance to shock, making them leading candidates for providing smaller, lighter, non- mechanical data-storage devices in place of hard disk drives. The versatility of EEPROM has already promoted significant growth in demand for the devices.

Toshiba invented flash memory, and has followed up its pioneering development work with a NAND-structure based flash memory. Toshiba believes that NAND offers a smaller memory cell and lower manufacturing costs than the NOR-structure flash memory. It also promotes efficient operation by allowing data read-out/input during data erasure, and erasure of any data block at any time.

Main features of the newly developed device:

  1. Data erasure can be done by individual block (8 kilobytes + 256 bytes), or multiple blocks, whereby and combination of two blocks to all blocks can be erased simultaneously. Single block erasure takes 2.5 milliseconds, while all blocks can be erased in only 5 milliseconds, a world record. If a program/ read operation is necessary during erase, a suspend/resume function stops the erasure until the program/read is fully executed, and then resumes erasure. This streamlines operation and increases overall efficiency.

  2. Data can be programed per page (512 bytes + 16 bytes) and average programming time per byte is approximately 0.4 microseconds. The chip can be completely rewritten in approximately 1.7 seconds, and program/read-out is automatically controlled inside the chip once an external command is received.

  3. Data read-out time is accelerated by an improved serial cycle, and can be achieved in 28 nanoseconds (serial access time).

  4. The new device has one 16-byte redundant cell per 256 bytes. It is used for such purposes as error correction control.

Main development points:

  1. Acceleration of serial reading operation: Reading operation time is the sum of cell access time for 528 byte cells (8.5 microseconds) and the serial access time per byte. Therefore, acceleration of the serial cycle is important for reducing total read-out time. In order to achieve a short cycle time for the read-out operation in the new device, a pipeline scheme was adopted that divides the serial operation into three stages: address count-up and column redundancy selection check; column select and data register output sensing; followed by data output from the output buffers. The new device achieves a 28-nanosecond serial access time.

  2. Accurate control of threshold voltage during program operation: Program operation consists of cell programing and verification of the programed state. Accurate control of threshold voltage distribution during programming is required in a NAND flash memory where memory cells are connected in series. A newly developed data register circuit is used in the device to simplify the programing operation, reducing the threshold voltage distribution width from 2.6V to 1.2V.

  3. Reduction of erase time: The erase block register of the new device allows any combination of blocks to be erased simultaneously. The complete erase operation consists of erase and verification of the state of the erased cell. If verification is conducted for each word line, the time required to verify the whole chip would be 95% of the total erase operation. In order to reduce total erase time, the new device can select all word lines for an erase block at the same time in the erase verify mode, achieving 2.5 milliseconds erase time for one block and 5 milliseconds for the whole chip.

Specifications
 
Process technology: 0.425 micrometer CMOS technology 
Memory cell:        Double polysilicon structure NAND memory 
                    cell 
Memory organization:(4M + 128K) x 8 bits 
Chip size:          7.14mm x 14.62mm 
Function:           Serial Data In/Data Out 
                    Auto Page Program 
                    Auto Block Erase 
                    Auto Multi-Block Erase 
                    Suspend/Resume 
                    Status Read 
                    Reset 
Function control:   Command control method 
Cycle time:         35 nanoseconds 
Program time:       0.4 microseconds (per byte) 
Access time:        28 nanoseconds (serial access time) 
Erase time:         2.5 milliseconds (1 block) 
                    5.0 milliseconds (Whole chip) 
Supply voltage:     Single 3.3V/single 5V 

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