Toshiba to Market New ASIC Series|
21 February, 1995
TOKYO -- Toshiba Corporation today announced a new series of application-specific integrated circuits (ASICs) that use 0.6 micrometer CMOS process technology and double- and triple-layer wiring technologies to realize high levels of integration and low power consumption. In practical terms, the new 5V operation TC190 series offers a usable gate count of up to 750,000; in terms of performance, power consumption is approximately 47% lower than that of Toshiba's 5V operation 0.8 micrometer process TC160 series ASICs and approximately 17% lower than that of the 5V operation 0.7 micrometer process TC170 series.
The new series is made up of two families: the TC190G series of gate arrays and the TC190C series of cell-based ICs. Toshiba will start accepting development orders for both series in April this year.
Portable computers that have to offer long battery life and workstations that must combine high processing speed with high performance CPUs have gradually migrated to 3.3V operation semiconductors. However, most desktop personal computers are built around 5V components, and require higher performance 5V operation ASICs. Toshiba's new ASIC series meet such demands.
ASICs are highly versatile semi-custom LSIs. Their master wafers carry basic circuits that can be wired to form semi- custom devices for particular functions, according to customer need and preferences. They provide a flexible, cost effective alternative to custom devices. The 1995 global market for ASICs is forecast at approximately $14.1 billion by value, up by 8% from 1994.
Main features of the new ASICs
(1) Use of 0.6 micrometer CMOS technology with double- and triple-layer interconnect technologies allow the TC190G series to offer a usable gate count of up to 700,000, rising to 750,000 in the TC190C series. Gate delay time is 0.26 nanoseconds.
(2) Improved power consumption is approximately 47% lower than in Toshiba's TC160 5V operation 0.8 micrometer process ASICs, and approximately 17% lower than in the TC170 series of 5V operation 0.7 micrometer process ASICs.
(3) TC190 series cell libraries offer full compatibility with those of the TC160 series and TC170 series, simplifying upward migration by users.
(4) Provision of a Peripheral Components Interconnect (PCI) buffer in the cell library simplifies design of peripheral circuits for use in high-speed PCs and engineering workstations incorporating a PCI-bus.
(5) CPGA (Ceramic Pin Grid Array), PFP (Plastic Flat Package), CFP (Ceramic Flat Package), PLCC (Plastic Leadless Chip Carrier), SVFP (Small Very Flat Package), TAB (Tape Automated Bonding)/TCP (Tape Carrier Package) packages will be made available. BGA (Ball Grid Array) that offer high-pin-count and high-dissipation will be also provided.
Specifications of the TC190 Series
Process technology: 0.6 micrometer Wiring technology: double- or triple-metal layer CMOS Si-gate Gate delay time: 0.26 nanoseconds (VDD = 5.0V, Fanout = 2 plus typical interconnect load) Supply voltage: Single 5V (4.75 - 5.25V) Maximum Usable Gates: TC190G series double-layer metal: 400,000 gates triple-layer metal: 700,000 gates TC190C series double-layer metal: 480,000 gates triple-layer metal: 750,000 gates
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