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IBM, Siemens, and Toshiba Alliance Announces Smallest Fully-Functional 256-megabit DRAM Chip

6 June, 1995

IBM Corporation
Siemens A.G.
Toshiba Corporation

Tokyo -- June 6, 1995 -- IBM Corporation, Siemens A.G. and Toshiba Corporation today announced a major achievement in their joint development project -- the smallest and fastest fully- functional 256-megabit memory chip ever developed and produced.

With a size of 286 square millimeters and a memory access time of just 26 nanoseconds, the revolutionary new chip is at least 13 percent smaller and has an access time that is nearly twice as fast as recently reported chips by other companies.

The smallest size and faster speed of the alliance device will help enable future memory-hungry systems such as powerful personal computers and workstations, as well as high-definition digital video, multimedia and telecommunications systems. For OEM developers, a smaller, faster chip means improved overall system performance and a reduced footprint for memory on printed circuit boards.

"Strategic alliances with world-class companies like Siemens and Toshiba are a significant part of our business srategy," said Dr. Michael J. Attardo, general manager of IBM's Microelectronics Division(tm). "The alliance put together a team of the best scientists, researchers and technicians anywhere, and its delivered world-class results. But this is only the beginning. The best is yet to come."

Jurgen Knorr, senior vice president of Siemens and head of its Semiconductor Group said, "The joint development has demonstrated that the best brains of the three companies can indeed create a leading-edge technology. This enables the companies to stay ahead of the fast moving progress in the semiconductor business even beyond the turn of the century."

"This remarkable breakthrough in advanced research shows what can be achieved by a dedicated alliance of companies that brings leading-edge capabilities to a highly motivated program with clear aims," said Masanobu Ohyama, senior vice president of Toshiba in charge of semiconductor operations. "The project and its achievements are clearly in the forefront of many internatinal projects for advanced semiconductors. I congratulate all involved."

DRAMs are pervasive, fingernail-size silicon devices that store electronic data in products ranging from mainframe computers to home appliances. A 256MDRAM can hold more than 25,000 pages of double-spaced (for Europe 16,000 pages 1 1/2 spaced) typewritten text, or the equivalent of the entire works of William Shakespeare, plus those of Johann Wolfgang Goethe, as well as the Manyoshu, the Kokinshu and the Tale of Genji. There still would be enough bits left to store a typical edition of the International Herald Tribune.

Researchers from the three companies have been working in a joint development program since January, 1993, at IBM's advanced Semiconductor Research and Development Center in Fishkill, New York. The innovative device, featuring 0.25 micron CMOS process technology, is the most latest in its achievements. It is designed to support any proposed Joint Electron Device Engineering Coucil (JEDEC) standard for 256MDRAMs, and is the most practical 256-megabit DRAM ever announced in the industry including its cell structure, chip size, and thus manufacturability.

Details of the performance and technology aspects of the chip will be presented at the 1995 Symposium on VLSI Technology (June 6 to 8), and at the 1995 Symposium on VLSI Circuits (June 8-10) both to be held in Kyoto, Japan.

The three-way alliance that developed the device is an outgrowth of separate, long-standing relationship among the companies. IBM and Siemens currently work together in 16Mb DRAM manufacturing. IBM, Siemens and Toshiba are partners in 64Mb DRAM development, and a joint venture between IBM Japan and Toshiba manufactures advanced color flat panel computer displays. Toshiba and Siemens have been collaborating in various semiconductor areas, including 1Mb DRAMs, standard cells and gate arrays.

All three companies have substantial experience in the field of sub-micron semiconductor development. Most notably, each has demonstrated technological leadership in 64Mb DRAMs, which is a key underpinning of the 256Mb chip.

Technical Supplement

Multibit Structure
The rapid pace of innovation of CPU speed and the high-speed processing requirements of such applications as color graphics is driving an industry trend for high-speed, multibit-type DRAMs that can transfer a large volume of data simultaneously over the databus between the CPU and the main memory.

The new device has a memory organization of 8M x 32 bit, and is ideal for meeting the industry trend. While 128-bit MPU is expected to be developed around the year 2000, just four 256MDRAM (8Mx32) chips can compose 128 megabyte memory with a 128-bit databus, instead of sixteen 16MDRAM (2Mx8) chips.

Flexible Redundancy Circuit
In general, standard DRAMs have redundancy circuits that rescue the functions of defective cells by spare cells. Conventional DRAMs are equipped with one reducancy circuit per 1-megabit memory cell unit, and if there are multiple defective cells within a 1-megabit unit, the redundancy circuit can only recover the function of a single cell. The new 256MDRAM has a flexible redundancy system, with eight collective redundancy circuits per 8-megabit unit of data. The system can recover up to eight defective cells regardless of their location within the 8- megabit unit, thus significantly improving the efficiency of recovering defective cells.

BEST Trench Cell
The trench cell with a self-aligned buried strap structure, or named BEST, is one of the first major technological achievements reported by the three companies in 1993. The cell is designed so that the "strap", an area which connects the trench capacitor and cell transistor, is automatically positioned and created at the time of wafer processing. The BEST cell is 25% smaller than a conventional trench cell. The cell size is 0.55 um x 1.1um, leading to the chip size of 285.5mm square, at least 13 percent smaller than devices with an equivalent density developed by other companies. the design will only need minor modifications or refinements before transfer to mass production.

DQ Pin on both Ends
This device features an original pin configuration, which spreads the positions of the data I/O pins and locate them at four corners of the package, rather than positioning them in concentration. This pin layout will contribute to smaller chip size and minimization of the signal delay due to decreased wiring duplication and reduced wiring length.


First fully functional samples of 256Mb DRAM jointly developed by IBM, Siemens, and Toshiba
Chip size:          285.5 square milimeters(13.25 x 21.55mm)
Technology:         CMOS
                    0.25 microns minimum feature
                    0.55 microns minimum pitch
Power Supply:       3.3V/2.5V
Organization:       64M x 4
                    32M x 8
                    16M x 16
                    8M x 32
Access Time:        26ns
Refresh:            8K cycle
Memory Cell:        Trench (Best) Cell
Cell Size:          0.605 square micron meters (0.55 x 1.1 micron)
Trench Capacitor:   35fF (femtofarad)
Trench Depth:       7 microns
Functions:          Fast Page Mode
                    Extended Data Out
                    Self Refresh

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