Tokyo -- Researchers at Toshiba Corporation's ULSI Research Labs have announced development of a new memory cell with an innovative trench capacitor structure. The cell brings closer the achievement of highly compact designs for future generations of dynamic random access memory (DRAM) with a capacity of 1 gigabit and more, and promises lower manufacturing costs than other memory cells.

Researchers have succeeded in using the new design to fabricate a memory cell with an area of 0.228 square microns, approximately 75 percent the size of the smallest cell yet reported.

Toshiba will officially present the new memory cell on December 13th, at the International Electron Devices Meeting, which will be held in Washington D.C. from December 10th to 13th.

Reductions in cell size by use of ever-finer sub-micron processing technologies results in a narrower capacitor. Maintaining sufficient capacitance to hold electrons (data) requires a compensatory deepening of the capacitor, but manufacturing a sufficiently narrow, deep structure has proved difficult. Toshiba has overcome the problem with the bottle-shaped design, which is narrow at the neck but wider in the area which holds the electrons. This innovative structure can be fabricated with only simple modifications to current processing technology. Utilizing the newly developed technology and processing technology for conventional trench capacitors -- without the need of any new processes -- researchers established that the bottle-shaped capacitor achieved a capacitance 1.3 to 1.5 times that of conventional trench capacitors with the same depth.

The trench capacitors of typical memories have a collar oxide layer fabricated on the sidewall of the capacitor opening to prevent electron leakage. Toshiba researchers utilized this basic design for the new capacitor. During an extended chemical dry etching process, the collar oxide layer prevents the etching of capacitor's sidewall at the neck, while the area below the neck is enlarged, thus creating the bottle-shaped cross-section. While the researchers had to modify the manufacturing sequence, they were able to utilize conventional processes, with no increase in their number. The design also required changes in some of the materials used in the fabrication process.

The transistor of the memory cell functions as a switch. The cells are controlled by bit lines and word lines which connect a series of cells aligned in a row. Current DRAMs utilize two vertical word lines and a horizontal bit line. This limits the theoretical minimum size of a memory cell to 8 square F, where F denotes the design rule in use. Toshiba's memory cell structure uses a single word line for two memory cells next to one another. As a result, one and half word lines and one bit line run through each memory cell. This cuts the theoretical minimum memory size to 6 square F, 75 percent of the previous limit.

Commenting on the new cell, Akimichi Hojo, General Manager of Toshiba's ULSI Research Labs, noted: "We are delighted that our innovations have brought us to the forefront in leading-edge semiconductor technology. We will accelerate development, with the goal of introducing more advanced semiconductors as early as possible."

Increased memory capacity without any increase in chip size is a central concern of DRAM R&D: small size is necessary to realize advanced generations of equipment, and to minimize manufacturing costs. Small chips with a 1-gigabit plus capacity require not only evolution in lithography, but the kind of innovation in design and development that Toshiba is exploring. A commercial 1-gigabit DRAM is expected to become available around the year 2000.

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Major specifications

Cell size	0.228 square micron meter
Capacitor structure	Bottle shaped trench capacitor
Design rule	0.18 micron CMOS processing

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Toshiba's new memory cell structure

Capacitor manufacturing process