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Toshiba's ATM Switch LSI Exchanges Data at 5Gbps -- the World's Fastest Rate

9 February, 1996

TOKYO -- Researchers at Toshiba Corporation developed a prototype switching LSI for asynchronous transfer mode (ATM) system, next generation high-speed data transmission network, that attains a data exchange speed of 5 gigabits a second with 8-input/8-output (622Mbps per port) -- the fastest rate yet achieved as a single CMOS chip. It is the world's first switching LSI to fully meet all the specifications proposed by the ATM Forum, the U.S.-based international consortium of ATM equipment manufacturers.

ATM networks are seen as the main data communication networks of the future, particularly for multimedia network. They use high speed switching to transmit multiple data of diverse content -- audio signals, image signals, text, voice, etc. along a single line at the same time, thus making more efficient use of networks. Data flows are broken down into cells made up of 48 bytes of information and 5 bytes of address data. Cells are individually transmitted in a prioritized order through high speed switching.

The addressing, prioritization and switching of each cell is handled by switching LSIs, the core control unit of an ATM exchange. Researchers of major electronics companies are racing hard to develop a switching LSI with a higher transmission capacity and the ability to move different types of data efficiently. Today, the transmission speed of the commercial level ATM switch LSI are in the range of 1Gbps to 2.5Gbps.

Priority Service for ATM Cell Transmission

Switching of multiple signals at the same time, requires the network to assign priorities in the order of cell transmission. For instance, more than one ATM cell might access the same port in the ATM switching LSI at the same time, but only one can pass through. Hence, priority has to be set in order to regulate the order of cell transmission effectively and achieve highly reliable as well as efficient data flow. Toshiba's prototype LSI is designed to meet 5 levels of "switching priority" according to the types of data transmitted. In addition, it supports 2 levels of "discarding priority" of the ATM cells, thus it fully supports the specification proposed by the ATM Forum.

From highest to lowest, the ATM cell switching priority are: CBR (Constant Bit Rate); rt-VBR (real time-Variable Bit Rate); nrt-VBR, ABR (Available Bit Rate); and UBR (Unspecified Bit Rate). For example, CBR transmission is used to assure real-time transmission of audio signals, where data delay are unacceptable while rt-VBR transmission is appropriate to transmit moving images, where data volumes vary greatly. ATM cells are discarded when their number surpasses the memory capacity of the LSI and its ability to maintain the total data flow. Discarded data are re-transmitted afterward.

The LSI's high performance achieving the full ATM-Forum specification, result from development of two innovative key elements: a high speed signal input/output interface, LVDS (Low Voltage Differential Signals), and a high- performance original address generator that functions as the core brain of the chip and supports multicasting to multiple ports without the need of an external dedicated LSI.

LVDS Interface

In order to realize a 5Gbps transmission capacity while lowering increased power consumption, Toshiba developed an LVDS interface for the LSI's input/output which can function reliably with a very narrow signal voltage amplitude. The lower amplitude level can reduce the time required for voltage charging and discharging, thus leading to high speed operation. Toshiba's newly developed LVDS interface is the industry's first with an amplitude level of only 0.4V. At this amplitude, the LSI operates at 200MHz, a frequency sufficiently high for 5Gbps data transmission.

Shift Register Type Address Generator An address generator forms the LSI's core control unit. It temporarily holds address information of each cell, transmitting them according to the priority it assigns to them along with their address information. Toshiba's shift register type address generator supports a buffer memory which can store up to 320 ATM cells. Toshiba's address generator also supports multicasting, enabling multicast transmission without the need of an external dedicated circuit, thus supporting high speed transmission.

The prototype LSI is fabricated utilizing 0.35 micron double layer metal CMOS technology. It integrates approximately 2 million transistors in a chip size of 17.4 mm x 17.4mm and is packaged in a 447-pin ceramic PGA package. It operates at 3.3V/2.5V and attains a power consumption level of 4W.

Mr. Kenshi Manabe, Technology Executive of Semiconductor Group, said: "ATM networks are among the most promising of advanced communication networks, and Toshiba is keen to support their development. I believe this new switching LSI put us in the forefront of ATM innovations."

The new technology will be officially announced at the International Solid State Circuits Conference, to be held in San Francisco from February 8th to 10th.

Major specifications

Process technology 0.35 micron double-metal CMOS
Transistor count 2.0 million
Die size 17.4mm x 17.4mm
Package 447 pin ceramic PGA (Pin Grid Array)
Power supply voltage 3.3V/2.5V
Interface CMOS/LVDS
Operating frequency Clock input: 25MHz, LVDS: 200MHz,Others: 50MHz
Power consumption 4W

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