Toshiba Develops Key LSI for Future Mobile TV Phone-Supports MPEG4 Video Encoding/Decoding Achieves Low Power Consumption of Only 60mW|
4 February, 1998
TOKYO-Toshiba Corporation today announced the prototype of a single-chip low-power video encoder and decoder LSI that will support future generations of power-sensitive wireless information terminals, including mobile TV phones. The LSI is the first in the world designed to support video signal encoding and decoding (CODEC) in the MPEG4 format, and has built-in software programmability that assures its compatibility with any revisions to the MPEG4 specification.
The Video CODEC LSI attains the high-level processing performance required for MPEG4 video encoding and decoding, even while achieving significant reductions in power consumption. A series of Toshiba-developed low-power technologies cuts power consumption to 60mW at 30MHz operation--an approximately 70 per cent improvement over the same chip without the technologies. The low-power design and the versatility of programmability assure that the LSI represents a major advance toward practical wireless information terminals supporting MPEG4 Video CODEC, including mobile TV phones.
MPEG (Moving Picture Coding Experts Group) is the international organization, jointly organized by ISO and IEC, that proposes formats for the compression of audio and video signals to assure their efficient storage and transmission. MPEG1 covers recording to such media as CD-ROMs, while the MPEG2 format sets standards for broadcasting and other audio and video equipment, like DVD. MPEG4 primarily targets wireless communication applications, and is currently being finalized by an ISO/IEC Joint Committee. Publication as an international standard is slated for February 1999. Toshiba is committed to making a major contributions to the finalization process, and its expertise in the technologies under discussion for MPEG4 have been applied to develop the prototype LSI.
A key element in defining the MPEG4 format is to determine a video signal compression format suitable for applications characterized by unstable data transmission, including wireless communications and the Internet. A key here is implementation of an error-correction function that prevents image degradation resulting from data-communication errors. Object-based coding of video images which enables, for example, editing and processing of objects in a picture separately from the background, is also under discussion.
Toshiba's prototype is compatible with the MPEG4 committee draft version 1, and is designed to support the H.263 format. This encoding and decoding TV conferencing format is recommended by the International Telecommunication Union, and its adoption for the MPEG4 format is expected. In the H.263 format, 10 QCIF picture frames (176 144 dot) are processed in a second at 30MHz operation.
The programmability of the LSI achieves the flexibility required for fine-tuning of the finalized MPEG4 specification, while its optimization of power consumption to the lowest level possible assures application in mobile communications terminals.
Incorporation of the embedded processor as the programmable processing core raises the LSI's total power consumption, as programmable processors normally consume more power than dedicated hardware circuits. However, Toshiba has cut consumption to the low level of only 60mW at 30MHz operation by applying four innovative architecture and circuit technologies: (1) Parallel operation of signal encoding/decoding to achieve a lower inner clock rate and power consumption, while maintaining overall processing performance; (2) Clock gating which brings the clock of unused program blocks to a halt state; (3) Variable supply voltage scheme and variable threshold-voltage CMOS, which lowers supply voltage without degrading performance; (4) Two levels of internal supply voltage, in which a lower voltage is applied to non-critical path circuits.
The prototype LSI was fabricated with 0.3 micron CMOS technology, and packs three million transistors on a nine millimeter square chip. Block design of the chip includes a core embedded processor, memory block, and hardware blocks that include the decoder, encoder and timing controller.
The technology will be presented at the International Solid-State Circuits Conference held from 5th to 7th of February at San Francisco, U.S.
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