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Toshiba Introduces 64-bit RISC Microprocessor With World's Lowest Power Consumption--only 1.2W

21 September, 1998

Tokyo--Toshiba Corporation today announced the first application specific standard product (ASSP) derived from its TX49 family of microprocessors based on the RISC architecture developed by US-based MIPS Technologies Inc. The new chip, TMPR4951F, will find its main applications in laser beam printers, set-top boxes and networking.

The TX49 64-bit microprocessor core of the new chip retains pin compatibility with Toshiba's TC86R4300F-100, but it has double the data cache capacity and transacts instructions 1.72 times faster. The LSI integrates SysAD bus as a system interface bus, supporting easy connection to external ASICs and memory devices. This performance is complemented by the lowest level of power consumption of any 64-bit RISC processor: 1.2W (@ 3.3V/ 133MHz). This is achieved by replacing the high-energy consumption, high noise dynamic circuit with a static circuit, but without any decrease in operating speed.

Toshiba offers a wide range of LSIs that combine logic circuits with core processors and embedded memories to form system-on-silicon solutions. They are offered as ASSP and as CPU cores for gate-arrays and cell-based ICs, and allow the company and its customers to achieve fast, cost-efficient design solutions for a wide range of systems and applications.

Samples of TMPR4951F will be available from October, at 3,500 yen. Monthly production of 20,000 units is slated for the 1Q 1999.

Key Features of TX49 Core
*Optimized 5-stage pipeline
*Upward-compatible Instruction Set
  • MIPS I, II and III Instruction Set Architecture (ISA)
  • Multiply and Add Instruction
  • Pre-fetch Instruction
  • *Built-in, high-capacity primary cache memory
  • Instruction cache 8k/16k/32kbyte (selectable)
    4 way set associative/ Lock function
  • Data cache 8k/16k/32kbyte (selectable)
    4-way set associative/Lock function
  • *Single or double-precision floating-point unit (option)
    *48 built-in double-entry joint-Translation Look-aside Buffer (TLB)
    *Low power consumption modes/ halt and doze modes
    *Power supply: 3.3V
    *Debug support unit: EJTAG

    Specification of TMPR4951F
    *CPU Core: TX49
    *Maximum Frequency: 133MHz
    *On-chip cache
  • Instruction cache: 16Kbyte
  • Data cache: 16Kbyte
  • 4-way set associative
  • Lock function
  • *Pre-fetch instruction
    *Memory management unit: 48 double-entry joint-Translation Look-aside Buffer (TLB)
    *Built-in SysAD interface bus
    *Support of non-blocking load
    *Power supply: 3.3V
    *Built-in debug support unit (DSU)
    *Package: QFP-120/ plastic package

    Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.

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