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Toshiba's New SRAM is Small, has Low Power Consumption Employs Full CMOS Technology

13 October, 1998

Tokyo--Toshiba Corporation today announced new static random access memories (SRAM) that combine significant chip shrinkage with a low standby current and a wide range of operating voltages. Fabricated with 0.35-micron millimeter, full complementary metal-oxide semiconductor (CMOS) process technology, the new SRAM are available in 2- and 4-megabit versions and are positioned to meet growing demand from the mobile equipment market. Toshiba will make its first samples available in October 1998.

SRAM support enhanced system operation by temporarily holding data for the CPU while it executes other tasks. Toshiba's new chips offers small, powerful SRAM packages with low standby currency, characteristics that are a must for enhanced performance and functionality in hand-held and portable products. The new devices are primarily targeted at such products as cellular phones, pagers and personal digital assistants, where smaller, more versatile SRAM will support further design innovation and better performance. The operating characteristics of the SRAM will also support wider use, in such applications as point-of-sales equipment.

Optimum Design for Stacked MCP
The new SRAM has pin alignments almost equivalent to flash memory, suiting it for incorporation in a stacked multi-chip package (MCP) with flash memory. It is available in three packages: thin small outline package (TSOP), with the same dimensions flash memory; renewed chip scale package (CSP) utilizing a ball grid array (BGA); and in stacked MCP, the new generation of MCP announced by Toshiba and other companies last month. Stacked MCP mounts SRAM and flash memory in a single package. It achieves a package shrink of 32% for x8-bit configuration and 37% for x16-bit configuration over the current MCP package, which mounts the SRAM and flash memories in parallel.

The new specifications and pin assignment were agreed by Toshiba and NEC and have been endorsed by several other semiconductor companies.

Specification of SRAM
* PackageTSOP40 pin for 2M/4M (x8 bit)
48 pin for 2M/4M (x16 bit)
CSP 48 balls (6 x 8/ ball pitch 0.75mm) for 2M/4M (x8/ x16 bit)
*Memory size: 2 megabit and 4 megabit
*Design rule: 0.35m CMOS process
*Bit configuration: x8 bit, x16 bit
*Access times: 85 and 100 nanoseconds
*Standby currency: 0.1mA (typical)
*Power consumption: 0.5m at 3V and 25
*Power supply voltage: 1.0V minimum
* Price and Sample availability

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