Toshiba Develops Prototype of Chain FRAM|
16 February, 1999
In Toshiba's prototype chain FRAM, each individual memory cell consists of a single transistor and a single ferroelectric capacitor in parallel, while a cell block consists of eight cells connected in series. This configuration achieves distinct advantages in performance and size over conventional FRAM.
In operation, the new FRAM achieves the world's fastest operating times, with a random access time of 37 nanoseconds and a read/write cycle time of 80 nanoseconds-a performance equivalent to a standard DRAM. The prototype chip is only 86% the size of current FRAM. Further miniaturization can be anticipated, as the chips stacked transistor design supports a theoretical reduction to 55% of the current size.
Toshiba also reported that the cell block can be expanded to a maximum of 16 cells, which will achieve further gains in performance.
FRAM are seen as having high potential, as they match the nonvolatility of flash memory while far surpassing it in operating speed. However, conventional FRAM connect the data-holding capacitor in series with the transistor. The result is a large cell size. Additionally, the conventional FRAM needs a separate driver for each capacitor, producing drive times longer than found in conventional DRAMs.
This chain FRAM prototype overcomes problems with conventional FRAM design and opens the way to high-speed, low-cost devices. Toshiba expects to see it widely used in such applications as mobile information equipment and IC cards, including e-money cards.
This prototype was officially announced at the International Solid State Circuits Conference, which is being held in San Francisco from February 15th to 17th.
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