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Toshiba Launches Low Power Consumption MPEG-4 Video Decoder LSI

11 December, 2000

Lower Power Consumption Achieved with 0.18μm
Process Technology and Embedded DRAMs

Tokyo--Toshiba Corporation today announced development of an MPEG-4 video decoder LSI with 4Mbit of embedded DRAM. Developed as a solution delivering video capability to mobile platforms, the new chip is derived from the fully integrated MPEG-4 videophone LSI Toshiba reported at International Solid-State Circuits Conference 2000 in February this year.

Toshiba has used 0.18-micron process, its most advanced semiconductor process technology, to shrink the new LSI to an easy-to-assemble Fine Ball Grid Array (FBGA) package of only 9 x 9 millimeters. The LSI integrates an MPEG-4 video decoding function and 4M of DRAM on a single chip and offers the reduced power consumption necessary for application in small mobile terminals.

Toshiba developed the new LSI to achieve a smaller, low power chip supporting all essential MPEG-4 decoding requirements. An improved architecture and reinforcement of the gated clock support achievement of motion picture playback at 50-milliwatt power consumption and 40MHz operation.

Toshiba positions the new chip as a core product in its system LSI lineup, and will seek further refinements in its power consumption and process technology.

Background of Development
Outline of New LSI
Specifications of New LSI

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