Outline of New LSI

  • Single-chip solution supports MPEG-4 video codec, in conformity with the latest industry specifications, AMR speech codec or audio decompression, and an audio and video multiplexer. The LSI also offers miniaturization and low power consumption in 3G-PP mobile phones and other mobile terminals.

  • Three 16-bit RISC-based processors, dedicated codec hardware and 12Mb of DRAM are supported; integration of a dedicated MPEG-4 video codec, AMR speech codec or audio decompression in a single chip cuts power consumption for wireless mobile terminals.

  • The new LSI has an interface for video data input and output supporting connectivity to CMOS image sensors and LCDs. This interface supports simplified system configuration and the miniaturization and low power operation of mobile terminals.

  • The new LSI can encode and decode QCIF (176 x 144) data at 15 frames per second when used as a videophone at 60MHz. It can simultaneously execute the AMR speech codec and H.223 audio and video multiplexer.

  • Pipeline architecture that processes data in parallel and a clock gating function (low power management) that switches off the clock of non-activating blocks cuts power consumption to 80mW during video conferencing at 60MHz operation. A kind of circuit structure can cuts off power supply to internal of the chip when no multimedia function is required.

Samples will be available in the second quarter of 2001 at US$50. Mass production will start from the fourth quarter of 2001. Toshiba positions the new chip as a core product in its system LSI lineup, and will seek further refinements in its power consumption and process technology.


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