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TOSHIBA ADDS 64-BIT MIPS-BASED MICROCONTROLLER WITH PCI INTERFACE

30 January, 2001


Tokyo--Toshiba Corporation today announced availability in production quantities of a new, higher-performance member of its MIPS-based microcontroller family that integrates a comprehensive array of on-chip peripherals. The 200-MHz, 64-bit TX4927TM microcontroller is a follow-on to the 32-bit TX3927TM chip, which is currently the most popular microcontroller in Toshiba's lineup. The wider bandwidth plus higher performance in the new IC will allow system designers to create a new generation of products ranging from digital multi-media, networks to printers, and the family commonality will allow rapid implementation of new designs and upgrades.

Toshiba's TX49/H2 processor core is optimized 5-stage pipeline with 64-bit data path based on MIPS architecture. 48-double entry Translation Lookaside Buffer (TLB) fully associative and Joint Translation Lookaside Buffer (JTLB) as a Memory Management Unit (MMU), hardware Multiply Accumulator (MAC), and single/double-precision floating-point unit (FPU) are incorporated. The 32-KBytes Instruction and Data caches are four-way set-associative. The instruction set supports MIPS I, II and III instructions, plus MIPS IV prefetch, multiply/ add and debug instructions.

An integrated SDRAM memory controller can handle max.100MHz four channels of Registered / Non registered DIMM SDR with ECC function, in configurations up to 2-GBytes. External Bus controller supports eight channels of ROM, Flash and Memory mapped I/O devices. The PCI bus controller supports either four 33-MHz or two 66-MHz bus masters. It fully complies with revision 2.2 of the PCI Local Bus Specification with PCI booting. DMA controller supports 4 independent channels and one channel for specialized PCI, 18 different sources interrupt controllers, 2 channels of UART, 3 channels of 32-bit timer/ counter, AC Link and 16-bit bi-directional parallel-IO ports.

Process, Power and Operation Temperature

The TX4927 microcontroller is built on Toshiba's 0.14-micron, 3.3V I/O / 1.5V Core process technology. At 200 MHz, it is targeted to consume only 1.5 Watt.
Commercial Temperature version is prepared and Industrial version will be followed.

Package

The TX4927 microcontroller comes in a 35 x 35 x 1.7mm, 420-thin ball-grid array with a 1.27-mm ball pitch.

Sample Price and Delivery

Samples will be available in May 2001 at 6,000 yen. Mass production will start from August 2001.


Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.

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