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Toshiba Announces World's First Image Recognition LSI for Intelligent Vehicle System

6 February, 2001


Versatility of a configurable media-processor demonstrated

Tokyo--Toshiba today announced the world's first image recognition LSI integrating a configurable media-processor. A version of the new LSI, customized for an intelligent vehicle system, was reported today at the International Solid-State Circuit Conference (ISSCC) in San Francisco.

Toshiba's new LSI realizes the new concept of a configurable media processor that enables optimization for a specific application by means of design-time configuration. Synthesizable RTL components are provided with the processor's template architecture, which can incorporate common components used in multiple applications and custom components for specific target applications. This versatility promises to introduce a high level of cost-performance into embedded solutions.

The application reported at ISSCC adopts advanced image recognition technology that isolates dynamic movement against its background. The application system is able to transact seventeen or eighteen real-time image frames a second, the level required to detect passing vehicles.

In practical terms, the new LSI monitors traffic in the outside lane when the vehicle in which it is installed is in motion. Mounted in a system board at the back of the vehicle, it tracks the approach of other vehicles up to the point where they draw alongside, including blind spots along the way. If the driver of the car with the LSI does something like switch lanes when a car is approaching at high speed, the standard visual image of the road is joined by a warning alarm.
The LSI can also be applied to other driving activities, such as crossing two lanes of traffic, monitoring the road ahead for obstacles, monitoring the driver's line of vision, and adaptive cruise control (ACC) that maintain a pre-determined distance between vehicles. In such applications as lane crossing and ACC, the processor can transact an average of 100 frames a second.

Toshiba expects to commercialize a monitoring system incorporating the new LSI within 2002.

Development Background

The cope of intelligent traffic systems (ITS) is widening from electronic toll-collection systems to cover overall driving safety, a move that has seen the commercialization of rear monitoring systems for installation in vehicles. However, current systems require a number of standard processors and offer a poor level of cost performance.

Toshiba has sought enhanced cost performance through advanced image recognition and customizable processor technologies, and their application to monitoring the road behind and beside the vehicle on which they are installed. The company also hopes that such advances in reliability will stimulate the market for ITS and contribute to a safer driving environment.

Outline of New LSI

  • The new LSI integrates a configurable media-processor developed for system LSIs that handle data-centric applications, such as multimedia, image processing, communications and audio processing. The media processor provides superior cost performance customization for each specific application.

  • The customizable media-processor integrates Very Long Instructions Word (*VLIW) architecture as an extension support. Various digital signal processors (DSP) can be realized by integrating a dedicated data path for each application. The present LSI uses the VLIW architecture to integrate a dedicated data path for transacting image recognition for the intelligent vehicle system. The processing unit consists of 3-way-VLIW and can process 32-bytes per cycle in parallel.

  • A memory of optimized size and structure is integrated as a result of the detailed analysis by the image recognition algorithm: 4-kilobyte (KB) instruction cache, 4KB data cache and 16KB two-banked scratch pad memory. In addition, direct memory controller is also integrated for direct interface between external memory and scratch pad memory. By parallel transaction of memory and processor, data access time of memory can be minimized.

  • In order to offer a competitive system of image recognition for the intelligent vehicle system, peripheral circuits are integrated, including Electric Erasable PROM controller, parallel I/ O, image data input unit and SDRAM controller. The SDRAM controller can be directly connected to 8MB of SDRAM operating at 125MHz.

*VLIW-an instruction contains several tasks.

Specifications of New LSI

Process0.25-micron four-layer metal
Logic and memory sizeapproximately 300,000 gates for random logic, 4KB instruction cache, 4KB data cache and 16KB data memory
Power supply3.3V (I/O), 2.5V (Internal)
Power consumption1.95W
Chip size7.1 x 7.1 millimeters


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