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Toshiba to Introduce 256Mb Fast Cycle RAM with the World's Fastest Random Access Time of 25ns

21 January, 2002

Tokyo--Toshiba Corporation today announced the introduction 256Mb fast cycle random access memory ICs (FCRAM) for applications requiring high speed, large capacity memory, including buffer memories for the switching systems in networks and routers. The company today started sample shipments of six ICs, including TC59LM806CFT-50 and TC59LM814CFT-50 with a sample price at US$60.

FCRAMs combine leading edge 0.175μm process technology and enhanced DRAM technology to achieve a large memory capacity and a fast random access time rivaling that SRAM. Narrowing the active memory area achieves low power consumption and an access time more than double that of present DRAM.

With the launch of its new FCRAM series, Toshiba offers state-of-art memory ICs that optimize high speed circuit technology to achieve a random access time of 25ns, the world's fastest, and a data transfer rate of 400 megabits per second at 200MHz operation, the world's highest.

Toshiba and Fujitsu jointly developed FCRAMs.
FCRAM is a trademark of Fujitsu Limited, Japan.

Background to Development

The rapid evolution of the Internet and LAN is seeing data transactions grow in volume and frequency, stimulating demand for high performance networks supported by large capacity, high speed memory switching and router systems. Shorter transaction times can be achieved if servers incorporate large capacity, high speed memory that can live up to the potential of broadband capacity. Toshiba's second-generation FCRAM are positioned to meet such market requirements. Demand for FCRAM is expected to reach 100 million units of 128Mb-equivalent IC by 2005, and Toshiba wants to play a key role in this promising market.

Major Features of New Products

  • Adoption of the same 2.5V power supply and stub series terminated logic (SSTL) -2 interface as DDR SDRAM simplifies design of memory controller.
  • Narrowing the memory active area cuts power consumption to approximately 30% less than current SDRAMs.
  • Variable-write length control controls write burst length by write commands. CAS latency-1 as write latency shortens turnaround time to make the data bus more efficient.

Major Specifications

Simulation Model

The new FCRAM devices will be supported by advanced simulation models developed by Toshiba in cooperation with Denali Software, Inc., a world leader in high performance memory subsystem design and verification. Detailed timing and behavior of memory devices during design and verification of new systems will be achieved through simulation with Specification of Memory Architecture (SOMA) files. For more information on Denali, please visit

Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.

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