Toshiba Enhances Embedded DRAM Performance with Breakthrough Silicon-on-Insulator Hybrid Wafer|
12 June, 2002
Tokyo--Toshiba Corporation today announced a breakthrough in embedding DRAM on silicon-on-insulator (SOI) wafers that ends the DRAM performance degradation typical of such integration. The new technology will be applied to high-performance system-on-chip (SoC) applications.
Performance enhancements of logic LSI for future broadband applications require integration of DRAM cells and a high performance processor on a single chip. Such a move will support high speed, wide bandwidth data transfers and improve overall system performance. However, embedding DRAM cells in an SOI wafer results in electrical characteristic inferior to those of DRAM on bulk wafers, as increased leakage current triggered by the SOI structure degrades data retention in the DRAM.
Toshiba's breakthrough hybrid wafer fuses the electrical characteristics of SOI and bulk wafer. The wafer's structure is achieved by removing part of the SOI layer and the buried oxide layer on SOI wafer and replacing it with conventional silicon by epitaxial-Si growth (SEG) technology.
The electrical characteristics of DRAMs embedded in the new hybrid wafers match that of DRAMs produced on bulk wafer with 180-nanometer (nm) CMOS process technology. Toshiba will introduce the hybrid wafer with 65nm process technology, currently targeted for 2005.
The technology, which is expected to play a crucial role in bringing SOI to SoC solutions, will be presented at the 2002 Symposium on VLSI Technology in Honolulu, Hawaii, from 11 to June 13, 2002.
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