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Toshiba to Introduce MPEG-4 Video Codec LSI for Mobile Applications

12 September, 2002


TC35280XB

Tokyo--Toshiba Corporation today announced an integrated MPEG-4 encoder and decoder LSI that provides a sophisticated, single-chip solution for high quality MPEG-4 video and audio in mobile systems for digital broadcasting and videophones.

TC35280XB integrates four dedicated reduced instruction set computing (RISC) processors. Two encode and decode MPEG-4 video and audio data and the others multiplex video and audio streams and filter noise from the video. The LSI also embeds 16 megabit (Mb) DRAM as working memory. Leading-edge 0.13-micron (micron) process technology assures low power consumption of 180 milliwatts for processing MPEG-4 video and audio at 125MHz.

Sample of TC35280XB will be available in the fourth quarter of 2002 at 4,000 yen. Mass production is slated for the first quarter of 2003 at 100,000 units a month.

Toshiba pioneered development of MPEG-4 codec and followed up development of the world's first dedicated LSI with several derivatives, primarily for mobile phone applications. High quality displays are now becoming an integral feature of more and more mobile products, spurring new demand for LSI that supports higher resolution displays while retaining the benefits of small packages and low power consumption.

Introducing the New LSI

  • Four dedicated RISC-based processors support encoding and decoding of MPEG-4 video, audio encoding and decoding, multiplexing of video and audio and filtering noises in the video signal.
  • The codecs and noise-filtering processors integrate dedicated circuitry for interfacing with the LSI's embedded DRAM and a CMOS image sensor and LCD.
  • The new LSI can encode and decode QCIF (176 x 144) data at 15 frames per second when used as a videophone at 60MHz, while simultaneously executing AMR speech codec and H.223 audio and video multiplexing.
  • When used as an MPEG-4 viewer or recorder, CIF data is encoded or decoded at 15 frames per second at 125MHz.
  • Pipeline architecture processes data in parallel and a clock-gating function (low power management) switches off the clock of non-activated blocks, cutting power consumption to 180mW at 125MHz operation. A kind of circuit structure can cuts off power supply to internal of the chip when no multimedia function is required.

Specifications

Specifications


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