TOSHIBA Top PageTOSHIBA Top Page
Latest releases Search by month Search by subject
Toshiba Reconfirms Leadership in 65-nanometer CMOS Process Technology With Lowest Power Consumption Transistor for Mobile Products

10 June, 2003


TOKYO--Toshiba Corporation today announced a major advance in 65-nanometer (nm) CMOS process technology that will bring high levels of performance and low power consumption to next generation LSIs for mobile products. Using a new gate dielectric material, Toshiba has developed a CMOS transistor that reduces gate leakage current to a level only 1/1000 that of CMOS transistors with conventional gate dielectrics. The company replaced the usual silicon dioxide in the transistor gate dielectric with nitrided hafnium silicate (HfSiON), a high dielectric constant (high-k) material, and confirmed its performance. Toshiba now plans to apply the new process to the mass production of system LSIs for mobile products in 2005.

Toshiba leads the semiconductor industry in the development of advanced process technology, including 90nm CMOS process technology for mass production of systems LSIs. Last December, Toshiba, with Sony Corporation, announced the development of the world's first 65-nanometer (nm) CMOS process technology for embedded DRAM system LSIs for high performance products. Today's announcement of a 65nm process technology suited to next generation mobile products, which must combine high-speed performance with low power consumption, confirms Toshiba's continuing lead in essential technologies for advanced generations of system LSIs.

Full details of the new technology were presented today at the VLSI Symposium in Kyoto, Japan.

The thickness of the gate dielectric in LSI grows progressively thinner with each new generation of CMOS process technology. However, that thinness can cause larger gate leakage current. This is emerging as a critical issue, especially in low power products, such as mobile terminals, and it has spurred a search for thicker gate dielectric materials offering the same performance as SiO2. HfSiON, nitrided hafnium silicate, is recognized as a promising material, but there are few reports of any practical fabrication process that can be applied to mass production. Toshiba has developed a fabrication process for HfSiON gate dielectric film for 65 nm low power CMOS applications and confirmed its characteristic with an experimentally fabricated LSI with 50nm gate-length CMOS transistors.

Three main achievements supported fabrication of transistors with the HfSiON gate dielectric:

1. Reduction of gate leakage current
Forming HfSiON gate dielectric with plasma oxidation and plasma nitridation reduces gate leakage to 1/1000 of that of SiO2, the present gate dielectric. This allows fabrication of low power CMOS transistors for mobile terminals.
   
2. Improved stability during CMOS fabrication
Various thermal processes are necessary for CMOS fabrication. The gate dielectric has to endure processes at temperatures at up to 1,000 degrees C. Forming HfSiON gate dielectric by plasma nitridation demonstrated high thermal durability at up to 1,050 degrees C without phase-separation or crystallization.
   
3. Fabrication of HfSiON gate dielectric CMOS transistor with sufficient drive current
Toshiba has fabricated CMOS transistors with 50nm gates with optimized HfSiON (EOT 1.2 nm). Sub-threshold characteristics demonstrate good characteristics and sufficiently high currents of 650 uA/um and 250 uA/um are achieved for n- and p-MOSFET, respectively, with gate leakage current only 1/1000 that of SiO2 gate dielectric.


Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.

Press Releases Top PageCopyright