| Toshiba Develops the World's First Embedded DRAM Memory
Cell Technology on Silicon-on-Insulator Wafer|
13 June, 2003
TOKYO -- Toshiba Corporation today announced that Toshiba has developed and verified the operability of the world's first memory cell technology for embedded DRAM system LSIs on silicon-on-insulator (SOI) wafers. Toshiba aims to apply the new technology to mass production of system LSIs for broadband network applications in 2006.
The move to ubiquitous computing -- total connectivity at all times -- relies on high-performance equipment. This in turn requires advanced system LSIs integrating ultra-high performance transistors and embedded high-density memory. One promising measure to dramatically raise transistor processing speed is fabrication of system LSI on a new-generation silicon substrate, silicon-on-insulator (SOI). However, the conventional DRAM cell structure is designed for conventional bulk wafers and it is difficult to produce embedded DRAM on SOI wafer.
Toshiba has experimentally fabricated a 96kbit cell array and verified the practical operability of the advanced cell structure with sufficient characteristics required for embedded DRAM system LSIs on SOI.
Full details of the new technology were presented on June 11 and 12 at the VLSI Symposium in Kyoto, Japan.
What is SOI?
Unlike a conventional bulk wafer, the SOI wafer comprises three layers: one single-crystal layer of silicon; a base silicon substrate; and a thin insulator, 1/1,000 the thickness of a human hair, that electrically insulates the single-crystal layer from the substrate, inhibiting waste electronic leakage to the substrate. The result is lower power consumption and higher processing speeds.
Toshiba succeeded in forming embedded DRAM system LSI on an SOI wafer by developing a new DRAM memory cell technology that makes use of the characteristics of SOI wafer itself, eliminating the necessity of capacitors where current DRAM cell stores data. The new memory cell technology, dubbed floating body cell (FBC), will be used for embedded DRAM system LSI for the 45-nanometer generation on.
Principle of Operation and cell structure
Conventional DRAM cell consists of a capacitor, where electric charge is stored, and a transistor that function as switches. The newly developed FBC does not have a capacitor and memorizes data by storing the electric charge in its transistor. Since the transistor works as both capacitor and electric switch, the cell area is half that of a conventional DRAM cell.
Compatibility in the manufacturing processes of DRAM cells and logic ICs is a crucial issue for the development of embedded DRAM cell technology for SOI-based system LSI. Toshiba's new process achieves full compatibility without any degradation in the performance of systems LSI. In order to ensure compatibility, poly-Si plug, a buffer layer of poly-silicon, is formed in contact area in memory cell.
Toshiba's experimental 96Kbit cell array achieved successful operation in all bits, a 36-nanosecond access time, 30-nanosecond data switching time, and 500-millisecond data retention time (at 85 degrees C). The results demonstrate that the new FBC technology can be applied to system LSI integrating DRAM cells with megabit or greater memory capacity.
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