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Toshiba's New Multi Chip Package Stacks Nine Layers in a Package Only 1.4mm High

21 January, 2004


Advances in Process and Mounting Technology Achieve
Thinner Chips and Improved Wire-Bonding in MCP

Toshiba's New Multi Chip Package Stacks Nine Layers in a Package Only 1.4mm High

Tokyo -- Toshiba Corporation today announced development of a Multi Chip Package (MCP) only 1.4mm high that stacks a total of nine layers of components. The new package draws on Toshiba's latest advances in process and mounting technology—the ability to fabricate memory chips only 70µm (micron) high, the thinnest chips yet developed for MCP application—to stack six memory chips with three spacers. The number of layers is a fifty percent improvement on the company's current state-of-the-art six-layer MCP and opens the way to more powerful and functional combinations of chips in a space-saving single package.

The new MCP can accommodate and combine a full range of memory chips, including SRAM, SDRAM, Psuedo SRAM, NOR flash memory and NAND flash memory, and typical applications can achieve a total capacity as high as 776 megabit (Mb). The flexibility offered by the MCP will support customers in creating powerful applications that enhance equipment performance while supporting circuit miniaturization. Toshiba will commercialize new MCP products based on the package in May this year.

Toshiba's latest process technology has realized a chip for MCP application that is only 70µm high, a full 15µm thinner than the company's present 85µm chips. This, and improved mounting technology, now allows the company to stack and wire nine layers, including six layers of memory chips, in the same 1.4mm high package that currently supports six-layer MCP. The new MCP also optimizes data transfers between the CPU and the MCP through adoption of a “triple-data bus system” that matches chip type to the right kind of bus. A high-speed bus supports SDRAM and NOR, a middle-speed bus SRAM and NOR, and a dedicated bus supports NAND.

At 11mm (W) x 14mm (D) x 1.4mm (H), Toshiba's new MCP is small, slim and powerful. It will bring higher capacity, denser memory capabilities to digital mobile equipment, including mobile phones with camera, while the ability to configure the most appropriate chips for specific applications will assure the delivery of optimized solutions and minimized power consumption. The May introduction of the new nine-layer MCP is expected to reinforce Toshiba's leadership in what is fast becoming the device of choice for advanced mobile phones and other personal digital equipment.

MCP Specifications (Sample)*

1. Chip Combination: six memory chips and three spacers (a total of nine layers)
2. Chip Type: SRAM (8Mb x 1), SDRAM (128Mb x 1), NOR Flash Memory (128Mb x 3), NAND Flash Memory (256Mb x 1)
3. Package Size: 11mm(W) x 14mm(D) x 1.4mm(H)
4. Power Supply: 1.8V
5. Ball Pitch: 0.65mm
6. Ball Counts: 225 balls
7. BUS Lines: Triple Data BUS System (Please see below)

MCP Specifications (Sample)*

* Above is typical sample and combination of chips can also include Psuedo SRAM if necessary.


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