| Toshiba Develops Key Technology for Advanced CMOS Fabrication|
16 December, 2004
TOKYO -- Toshiba Corporation today announced a new method for suppressing thermal instability and current leakage in MOS transistors that supports advanced CMOS fabrication at 45-nanometer gate lengths and beyond. The new technology will contribute to the continued application of CMOS technology to future generations of LSI.
The conventional NiSi layer in a shallow junction is thermally unstable; subjecting the layer to heat results in large current leakage. Toshiba has developed a method to suppress this thermal instability that is based on implanting fluorine ion into the surface prior to the formation of the NiSi layer. This solution directly addresses a significant problem in the LSI manufacturing process, and offers a solution for advanced CMOS fabrication with NiSi.
The new method also offers a cost-effective solution, since implantation of fluorine ion can be done with current manufacturing equipment and produces no adverse side effects in the manufacturing process, such as sharp increase of sheet resistance.
As lower power consumption while delivering greater performance is a prerequisite for advanced MOS transistors, especially process technology at 45 nanometer and beyond, Toshiba plans to incorporate the new method into 45-nanometer LSI fabrication process.
Full details of the new technology were presented on December 15 at the IEDM 2004 in San Francisco.
Figure 1. Leakage mechanism - diffusion of atomic Ni against heat stimulus
Figure 2. Leakage suppression - effect of implanting fluorine ion
|Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.|