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Toshiba's New SoC Design Platform Shortens Turn-Around-Times

26 January, 2005


Universal Array Reduces TAT for 130nm, 90nm Process Technology & Beyond

Tokyo -- Toshiba Corporation today announced Universal Array, a new system-on-chip (SoC) design platform that significantly reduces the development time for SoC devices. By applying Universal Array, Toshiba has cut the turn-around-time for production of engineering samples for 130nm and 90nm process technology significantly.

All cell-based IC have to undergo a rigorous verification and testing process prior to production, a process that is as essential as it is time-consuming. Conventionally, once the design process reaches tape out, the point where EDA tools can be applied to production of engineering samples of ICs, the diffusion wafer (DW) that integrates the basic IC components is fabricated, and the wafer then undergoes personalization (personalized wafer, PW) to complete the manufacturing process. Universal Array shortens this process time by allowing fabrication of the DW at the same time as the implementation and timing verification processes.

"Universal Array is a cost-effective solution that brings advanced flexibility to the SoC development and verification process," said Takashi Yoshimori, Technology Executive, SoC-Design of Toshiba's Semiconductor Company. "This fast and flexible SoC development platform will allow us to offer customers faster turn -around-times and support them in responding to market needs with differentiated digital products."

Toshiba will apply Universal Array to the production of engineering samples of TC280 series (130nm) in the first quarter of 2005 and plans to extend application to the TC300 series (90nm) in the second quarter.

Toshiba will present Universal Array and its design results at EDS Fair 2005 in Yokohama, Japan on January 27 and 28.

((TAT of ES with implementation of Universal Array))

TAT of ES with implementation of Universal Array
* SC: Standard Cell (cell-based IC)
* UA: Universal Array
* DW: Diffusion Wafer
* PW: Personalized Wafer

((Outline of TC280 Series with Universal Array))
1) Process: 130nm CMOS process (Gate Length: 110nm)
2) Supply Voltage: Core: 1.5V, IO: 2.5V / 3.3V
3) Primitive Cells:
- Lineup : Compatible with TC300C (90nm process)
- Density: 176K Gate/mm2
- Delay: 17ps (LP type), 13ps (HS type) (IV x 4 type cell, FO=1)
- Power: 14nW/MHz/Gate (IV x 1 type cell)
4) IO Cells: Same as TC280C
5) Memories: Same as TC280C
6) IPs: Same as TC280C
7) Engineering Sample: 1Q 2005


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