Press Releases-1 21 September, 2005 | News

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Toshiba Sales of High-speed 32-bit CISC Microcontroller

21 September, 2005

-Outperforms predecessors by a factor of three-
-Rich array of built-in peripheral circuits supports
numerous applications requiring high-speed processing-

Tokyo--Toshiba Corporation today announced a 32-bit CISC (complex instruction set computer) microcontroller that delivers high-level processing capacity and low power consumption. Sample shipment of the microcontroller, TMP92CZ26XBG, will start in December, with mass production following in the first quarter of 2006.

TMP92CZ26XBG employs 0.18µm process technology to mount the "900/H1" high-speed 32-bit CPU core. The chip's internal clock operates at 60MHz, realizing a processing capacity of approximately 30 MIPS¹ and a low power consumption of approximately 60 mW².

The new microcontroller also integrates on-chip large capacity RAM with a short access time, allowing the CPU to maximize processing capacity. Support is provided for a wide variety of audio CODECs and graphics and other applications that previous CISC microcontrollers did not support.

Toshiba has also integrated additional IP into the CPU as peripheral circuits—controllers for a color-ready LCD, USB device and NAND Flash memory—configuring a microcontroller ideally suited for mobile devices, such as electronic dictionaries.

Sample shipment will start in December at a price of 2,000 yen. Mass-production will begin in the first quarter of 2006 at a monthly volume of 30,000 units.

TMP92CZ26XBG will be exhibited at CEATEC JAPAN 2005, from October 4 to 8 at Makuhari Messe, including a demonstration of the microcontroller's ability to run text to speech (TTS) software in real-time.

Development Background
As the performance of mobile devices continues to improve by leaps and bounds, there is increasing need for microcontrollers able to quickly process large volumes of data yet operate with low power consumption.

To meet these needs, Toshiba used 0.18µm process technology to develop the TLCS-900/H1 CPU core that operates at an internal clock rate at 60 MHz. The new CPU core has a processing capacity approximately three times that of the company's previous products, while achieving lower power consumption. By building-in key peripheral IP for a color-ready LCD controller, USB device controller, and NAND Flash memory controller, Toshiba brings to market a microcontroller expressly designed for application in mobile devices.

Main Features of the New Product

1.	Application of 0.18 m process technology and the newly developed high-speed 32-bit 900/H1 core allowed Toshiba to achieve a CPU with an internal clock speed of 60 MHz and a processing performance approximately three times that of the previous 900/H1 core.
2.	Accelerated CPU performance is enhanced by memory interleaving and on-chip large-capacity RAM (288 KB) with short access times.
3.	The new chip offers instruction code compatibility with Toshiba's TLCS-900 series of 16-bit original processors, the 900/L, 900/L1 and 900/H cores. As with the TLCS-900 families, Toshiba realizes high code efficiency by using Toshiba's own C compiler.
4.	The on-chip SDRAM or NAND flash memory controller offers outstanding bit-unit cost performance and allows customers to development products with reduced set costs. For NAND flash memory controllers, the TMP92CZ26XBG allows access to multi-level cell NAND flash memory, which is a new technology.
5.	A built-in 256-/4096-color color STN or a TFT-ready LCD controller can handle a maximum of 16 million colors and supports configuration with a high-quality color display.
6.	This product has an on-chip MAC (Multiply and Accumulate Calculate unit) that performs high-speed 64bit+ (32bits x 32bits) processing.

Main Specifications of the New Product

^1.	Measured using a Toshiba-original benchmark test.
^2.	On-chip RAM operation at room temperature, running 1.5 V.

Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.