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Toshiba Develops World's Fastest, Highest Density FeRAM

7 February, 2006


64-megabit density combined with read and write speed of 200-megabytes a second

TOKYO--Toshiba Corporation today announced a newly developed FeRAM—a Ferroelectric Random Access Memory—that redefines industry benchmarks for density and operating speed. The new chip takes FeRAM storage to the 64-megabit level and pushes read and write speed to 200-megabytes a second, the most advanced combination of performance and density yet achieved.

Fabricated with 130-nanometer CMOS process technology, the 64-megabit FeRAM is based on Toshiba's chainFeRAMTM architecture, which significantly reduces memory cell size. It also integrates optimized circuitry designed to reduce the circuit area and squelch noise during read operation, and ECC, a high-speed error checking and correcting circuit that assures data reliability at high speed operation, even in severe operating conditions.

The key to the performance boost is adoption of burst mode for high-speed data transfers. Its successful integration pushes read and write speed to 200-megabytes a second—the fastest speed of any FeRAM.

FeRAM combines the fast operating characteristics of DRAM and SRAM with flash memory's ability to retain data while powered off, characteristics that continue to attract semiconductor industry attention. Toshiba will continue its R&D in FeRAM, aiming for eventually use in a wide range of applications, including high-performance mobile digital equipment and computers.

Full details of the new FeRAM were presented on February 6 at ISSCC (International Solid-State Circuits Conference) 2006 in San Francisco, USA.

Outline of new technologies:
1) Increasing miniaturization of the fabrication process results in reduced control voltage in the memory cell, making it more susceptible to noise. Miniaturization also requires finer wiring, another potential source of noise. The 64-megabit FeRAM employs a new wiring design in which neighboring wirings operate in sequence; one is off when the other is on. This allows off lines to provide a noise barrier between on lines.

New circuit design (pattern diagram)
New circuit design (pattern diagram)

2) Write data reliability is enhanced by ECC, an error checking and correcting circuit that detects and corrects write data errors. The new FeRAM also adopts a new control method that uses pseudo writing processing during error correction and that carries our write and error operations in parallel. This approach minimizes increases in write processing time resulting from error correction operation, cutting it to approximately 15% instead of approximately 30%.

3) The new FeRAM adopts burst mode transmission, sending collected data in high-speed bursts to realize a read and write speed of 200-megabytes a second. This is a world record for FeRAM.

Main specifications:
Process:   130 nanometer CMOS
Density:   64 megabits
Cell size:   0.7191 um2
Cycle time:   60 nanoseconds
Read/write speed
(bandwidth):
  200 megabytes/second
Power supply voltage:   3.3V, 2.5V

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