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Toshiba Develops Low Power Consumption Technology for Embedded DRAM for 65nm Generation System LSI

9 February, 2006

Reduces standby power consumption to approximately one eighth

Tokyo--Toshiba Corporation today announced a new approach to reducing the power consumption of embedded DRAM for 65-nanometer System LSI. The new technology cuts the standby power consumption of embedded DRAM to approximately one-eighth.

DRAM cells are volatile memories that must be refreshed with a periodic electric charge to retain stored data. Any solution that reduces the refresh rate will promote reduced power consumption.

Toshiba adopted a two-fold approach to improving embedded DRAM power efficiency, introducing redundancy circuits that rescue data in defective cells, and error checking and correcting (ECC) circuits, into the DRAM design. This combination raised error tolerance from 1.5ppm to 150ppm, an increase of 100 times that allowed data to be retained in DRAM cells even with a refresh rate cut to one-eighth of the usual rate.

Toshiba fine-tuned this approach by optimizing the chip control algorithm to manage reduced refresh operations only during standby mode. This assured that the embedded DRAM retains the overall operating performance of equivalent embedded DRAM without the new approaches.

Accelerated operating speed, high level data reliability and lower power consumption are the essential requirements for high performance embedded DRAM for system LSI. Toshiba's latest advance secures all three goals, and the company will continue to refine the technologies for high performance system LSI.

Full details of the new technology were presented at ISSCC (International Solid-State Circuits Conference) 2006 in San Francisco, USA.

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