Toshiba’s New Variability Aware Modeling for Design Layout to Boost Gate Density
19 June, 2008
New technique for next-generation 45nm CMOS technology boosts gate density to 2.6 times higher than that of 65nm CMOS technology
TOKYO--Toshiba Corporation today announced that it has developed a new compact model for circuit design that achieves higher gate density and improved cost-performance in next-generation 45nm CMOS technology. By applying this technique, gate density for 45nm CMOS technology is boosted to 2.6 times higher than that of 65nm CMOS technology, and surpassing the gain of 2.0 times that is the typically expected technology trend in generational migration.
Circuit design layout, particularly proximity (proximity effect), is the dominant factor in the variability of transistor performance, and gate density also plays an important role in chip cost. By applying this technique to the design in 45nm CMOS technology, Toshiba achieves both high performance and cost competitiveness in system LSI.
The newly developed technique was reported on June 18th at Session 9.3 of Symposia on VLSI Technology 2008, in Honolulu, Hawaii, USA.
Toshiba has developed the new technique, which predicts the performance of each transistor individually, by focusing on factors dependent on circuit layout. In 65nm CMOS technology, gate length, gate width and the distance between the gate and isolation area (see Fig. 1) are considered in design, as major factors affecting transistor performance. In advanced 45nm CMOS technology and beyond, additional factors such as the space of gates and locations of contacts (see Fig. 2) are modeled and fed into the design. Toshiba's new technique estimates each transistor characteristics and feeds them into the circuit design. As a result, Toshiba has achieved higher gate density without increasing the margin for variability in design.
Advances in process technology have required shorter gate lengths in CMOS process technology, and application of stress enhancement techniques*1 has proved effective as a means to improve transistor performance. However, from the 45nm CMOS generation, gate length scaling will advance significantly, and the application of stress enhancement techniques will produce complicated variability as a result of dependence on layout in the design. This issue could be evaded in earlier generations by setting an additional design margin for safer design or by restricting the pattern and design. However, this approach sacrifices improvement in gate density and is insufficient for the 45nm CMOS generation and beyond.
*1 Stress enhancement technique:
Fig. 1 Transistor factors dependent on circuit layout
Fig. 2 Transistor factors dependent on circuit layout
Fig. 3 Advanced process technology and transistor gate density
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