3D transistors such as fin field-effect transistors
(FinFETs) are promising device structures for nextgeneration
logic LSIs, because they can reduce off-state
leakage current and power consumption. However, a
design guideline for a strained silicon channel in FinFETs
to increase on-state drive current for high-speed LSI
operation has not yet been clarified.
Toshiba has proposed a 3D stress engineering method
in which transverse stress along the fin-width direction
and vertical stress along the fin-height direction are
introduced in addition to longitudinal stress along
the gate-length direction of the FinFET. We have
systematically measured the changes in carrier mobility
by mechanically applying uniaxial stress to FinFETs, and
clarified the types of stresses that should be applied along
each direction to enhance mobility in n-type and p-type
FinFETs.
This work was partly supported by the Innovation
Research Project on Nanoelectronics Materials and
Structures of the Ministry of Economy, Trade and
Industry (METI).
LSI: Large-scale integration
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