Tokyo--Toshiba Corporation today announced two additions to its TX49 family of high performance RISC microprocessors derived from architecture developed by US-based MIPS Technologies Inc. The new chips, TMPR4955F and TMPR4956F, employ a new core, the TX49/H, that surpasses the operating speed of its predecessor, the TX49. Both are fabricated with advanced 0.25 microns process technology and have a multiple metal-layer design supporting chip shrink. The microprocessors are available in 167 megahertz (MHz) and 200MHz versions and will find their main application in laser beam printers, set-top boxes and networking products.

Connection to external ASICs and memory devices is supported by a SysAD bus system interface, while a Floating Point Unit (FPU) co-processor supports complex transactions, such as processing large 3D graphics data files. At 200 MHz operation, TMPR4955F-200 and TMPR4956F-200, can handle such graphics 170 percentage (%) faster than Toshiba's current top-of-the-line derivative, TMPR4951-133. The new processors also offer double the data cache memory capacity and lower power consumption: 1.8W at 200MHz; 2.5V for CPU operation and 3.3V for I/O operations. A debug support unit (DSU) is also incorporated in the design. It sets a breaking point in system operation to check data in the cache memory and resistor, supporting real-time data analysis.

Toshiba offers a wide range of ASIC-based LSI that facilitate the combination of logic circuits with core processors to form computer-on silicon (COS) solutions. This fusion of computer-system technology and silicon technology meets diverse demands for system-based applications.

Schedule

Specifications of TMPR4955F

• Process: 0.25 microns, four-layer metal
• Power supply: 2.5V for CPU and 3.3V for I/O
• Power consumption: 1.8W at 200MHz
• Operating frequency: 167MHz and 200MHz
• On-chip cache

  Instruction cache: 32Kb

  Data cache: 32Kb

  4-way set associative

  Lock function

• Memory management unit: 48 double-entry joint-Translation Look-aside Buffer (TLB)
• SysAD bus: 32 bit bandwidth
• Protocol of SysAD bus: compatible to R4600, R4700 and R5000
• FPU: Single or double-precision floating-point unit in conformity with IEEE754
• Package: QFP160-pin plastic package

• Process: 0.25 microns, four-layer metal
• Power supply: 2.5V for CPU, 3.3V for I/O
• Power Consumption: 1.8W at 200MHz
• Operating frequency: 167MHz and 200MHz
• On-chip cache

  Instruction cache: 32K byte

  Data cache: 32K byte

  4-way set associative

  Lock function

• Memory management unit: 48 double-entry joint-Translation Look-aside Buffer (TLB)
• SysAD bus: 64 bit bandwidth
• Protocol of SysAD bus: compatible to R4600, R4700 and R5000
• FPU: Single or double-precision floating-point unit in conformity with IEEE754
• Package: QFP208 plastic package