TOKYO--Toshiba Corporation today announced a highly integrated, scalable Asynchronous Transfer Mode (ATM) switch chipset that provides a highly effective solution for implementing complete ATM functionality in high-performance switching systems. The chipset is targeted for use in ATM Wide-Area Networks (WAN) edge networking equipment, such as access/concentrators, multi-service edge switches, Digital Subscriber Line Access Multiplexers (DSLAM), and IP router WAN access cards.

Toshiba's chipset comprises three devices: the Switch Element (SE), TC35880TB; the Switch Access with Multiplexer (SAM), TC35881TB; and the Distributor/Arbiter (DA), TC35882TB. Different combinations of these devices allow various configurations that support switching levels ranging from 622Mbps to 20Gbps. The chips are interconnected to each other by the industry standard Low Voltage Differential Signal (LVDS) bus, and the LVDS bus control circuits are embedded into each chip.

The chipset features a broad range of traffic congestion and switch management functions to maintain optimum performance under varying conditions. Five quality-of-service (QoS) classes are supported: constant bit-rate (CBR), real-time variable bit-rate (rt-VBR), non-real-time variable bit-rate (nrt-VBR), available bit-rate (ABR) and unspecified bit-rate (UBR). The chipset also incorporates functionality for 32 shapers, flow control, scheduling and per-VC queuing.

The highly integrated SAM performs the majority of switching and traffic management functions. While the SAM is capable of operation as a standalone ATM switching node at 622Mbps, a switch fabric consisting of a single SE device is required for architectures from 622Mbps to 5Gbps. For solutions requiring performance beyond 5Gbps, multiple SEs and DAs are utilized. A 5Gbps, 8 x 8 (OC-12/link) implementation requires only eight SAMs and one SE.

The SAM and SE are manufactured in 0.3 micron CMOS and the DA is manufactured in 0.4 micron CMOS. All devices operate at clock frequencies from 25MHz up to 200MHz with 3.3V supply voltage and are packaged in Tape Ball Grid Array (T-BGA) packages.

ATM networks are key elements of high speed, high capacity data networks. They support high speed switching of multiple data with diverse content--audio, images, text and voice--along a single line at the same time, thus making more efficient use of networks. Data flows are broken down into cells of 48 bytes of information and 5 bytes of address data. Cells are individually transmitted in a prioritized order through high speed switching. The addressing, prioritization and switching of each cell is handled by the switching LSIs, the core control unit of an ATM exchange.

Samples of Toshiba's complete chipset are available now, with volume production anticipated in the fourth quarter of 1999.