Leading edge 0.16-micron process technology
achieve a 60-nanosecond access time

Tokyo--Toshiba Corporation today announced new, high performance 64-megabit and 128Mb NOR flash memory ICs that achieve a 60-nanosecond random access time, the fastest of any commercialized NOR flash memory. Both ICs are fabricated with leading-edge 0.16-micron process technology, have built-in page mode and support simultaneous read during write or erase.

Demand for NOR flash memory is growing in two key areas, set top boxes and mobile products. Recent mobile phones incorporate more application software and its successful operation requires high speed, high capacity NOR flash memory ICs. This need underpins Toshiba's decision to develop high capacity chips with cutting-edge system performance enhancements, including built in page mode and simultaneous read during write or erase.

Toshiba will mass produce the 64Mb and 128Mb ICs, at a level of 400,000 and 200,000 units a month, respectively, at Yokkaichi Operations, its main facility for manufacturing memory devices. The addition of these high performance, high capacity devices to its current product line-up will enhance customer choice and reinforce Toshiba's position in the NOR flash memory sector.

Key features of New NOR Flash Memory ICs

• The world's fastest random access time, 60ns, and a 20ns page access time are supported by 0.16μ process technology.
• Operating current is low, despite high-speed operation: 55mA during random access, 5mA in page mode, and 15mA in write and erase mode.
• Page mode and simultaneous read during write or erase support the need for mobile phones with a minimized overall system operation time.

The 64Mb chip will be available in a 48-pin thin small outline package (TSOP) and the 128Mb chip in a 56-pin TSOP for set top box application. The chips will also be stacked in multi-chip packages (MCP) with SRAM and Pseudo-SRAM for space-limited mobile products.

Major Specifications of 64Mb and 128Mb NOR Flash Memory ICs

• Design Rule: 0.16μ process technology
• Operating Voltage: VCC=2.3 - 3.6V
• Random Access Time: 60ns at 2.7V/ 70ns at 2.3V
• Page Access Time: 20ns at 2.7V/ 25ns at 2.3V
• Page Size: eight words per page
• Operating Current: 55mA during random access; 5mA at page mode; 15mA in write and erase mode; 10mA in standby mode
• Package: 48pin TSOP-I (64Mb); 56pin TSOP-I (128Mb); Stacked MCP (64Mb and 128Mb)
• Major Functions: auto program mode; chip erase mode; block write and erase operation; simultaneous read during write or erase; and page mode
• Block Erase Configuration:
  
• Memory Bank Configuration: four banks (1:3:3:1)
  8M:24Mb:24Mb:8Mb for 64Mb NOR flash memory IC
  16Mb:48Mb:48Mb:16Mb for 128Mb NOR flash memory IC
• Program and Erase Cycles: guaranteed minimum 100,000 cycles