TC81240TB, back-end LSI, integrates CPU, MPEG-2 decoder and graphic function

Tokyo--Toshiba Corporation today announced that it has integrated the key LSIs for the back-end system of digital televisions in a new single-chip solution, TC81240TB. The new LSI brings together upgraded versions of Toshiba's CPU and MPEG-2 decoder for digital TVs, along with the company's graphics LSI and a second CPU to maximize system efficiency.

The new LSI processes signals compressed by MPEG-2 technology and reproduces high definition motion pictures and sound. Built-in interfaces, including USB, support connection to other digital consumer products.

The second CPU, developed with Toshiba's Media embedded Processor (MeP) technology, is a configurable processor that is used to control MPEG-2 decoding for enhancement of overall system operation.

Samples of the new LSI are now available at 8,000 yen. Mass production is slated for this summer at monthly 50,000 units. Evaluation tools including reference boards and driver software are available.

Background of Development

Digital broadcasting is the future of television. In Japan, broadcasting satellite (BS)-based digital broadcasts started in December 2000, and the 110 communication satellite (CS)-based digital broadcasting follows. Terrestrial digital broadcasting will start in 2003, and provide a further stimulus to a total transition to digital system. Toshiba initially supported digital TV makers with three ICs for the back-end system of digital receivers that are now integrated in TC81240TB.

Upgraded Functions

• MPEG-2 decoding capability: simultaneous decoding of two HD channels.
• CPU operating frequency: upgraded from 32-bit 133MHz to 64-bit 200MHz.
• Additional interfaces: USB interface.
• Support for DDR-SDRAM.
• Adoption of unified memory architecture.

Outlines of New LSI

• Supports key broadcasting systems: BS digital broadcasting, 110 CS digital broadcasting and digital terrestrial broadcasting in Japan; and Advanced Television Systems Committee, digital terrestrial broadcasting in U.S.
• Integrates MIPS-based CPU: 230 MIPS at 200MHz operating frequency.
• Memory interface: Support of up to 512MB 100 and 133MHz DDR-SDRAM.
• Trans-stream processor: Three data streams can be input and executed simultaneously.
• MPEG-2 decoder: Simultaneous decoding of two broadcast signals, one of them high definition. In TVs that display two channels at once, adjusting the size of the images allows simultaneous decoding and transmission of two high-definition signals.
• Video encoder: Integration of six DAC (three for main channels, three for VCR).
• Audio decoder: Integration of original DSP for Audio, AAC and AC3.
• Package: 648-ball Thin Ball Grid Array (TBGA).