Tokyo -- Toshiba Corporation today announced partial frequency/voltage regulator, a new technology that reduces system LSI power consumption during operation by optimizing the operating frequency and supply voltage at the module level. This revolutionary approach allows optimization of the power consumption of each individual intellectual property (IP) integrated into SoCs, producing an overall decrease in consumption. Toshiba achieved 40 present power-savings on operating module of test chip (media-embedded processor base) for mobile multimedia application by implementing the new technology.

As mobile multimedia SoC advance in functionality and scale, measures to curb leak current and power consumption are among the biggest challenges for system LSI engineers. Toshiba has already promoted a partial solution to this problem with the development and deployment of selective multi-threshold (MT) technology, which reduces leak current and cuts standby power consumption. Partial frequency/voltage regulator complements this to reduce operating voltage.

By integrating both selective MT technology and partial frequency/voltage regulator into SoC, Toshiba has realized an innovative SoC design platform for power management and transistor leakage control and it will apply the platform to future generations of devices. The end result will be seen in lower power consumption in mobile applications, such as cellular phones and digital still cameras.

"Development of this new technology really allows us to make an important contribution to overcoming power consumption limitations with a modular dynamic-voltage and frequency scaling architecture," said Takashi Yoshimori, Technology Executive, SoC-Design of Toshiba's Semiconductor Company. "once we have made this new design platform a standard part of our low power design methodology, we will be able to offer improved device performance to our customers."

Toshiba will present the new design platform and design results at EDS Fair 2005 in Yokohama, Japan on January 27 and 28.